1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and in particular, to a twin cell DRAM (Dynamic Random Access Memory) storing data of one bit with two memory cells. More specifically, the present invention relates to a layout of memory cells in a twin cell mode DRAM.
2. Description of the Background Art
In a DRAM, a memory cell is generally configured of one selection (access) transistor and one capacitor, and data is stored in the capacitor in the form of charges. An electrode node storing the data of the memory cell capacitor is referred to as a storage node. Charges corresponding to data are accumulated at the storage node. An electrode facing this storage node is referred to as a cell plate electrode and receives a voltage of a prescribed level.
In data reading, the charges accumulated in the capacitor is transferred to a bit line via the selection transistor of the memory cell. A voltage of the bit line is then amplified by a sense amplifier.
A folded bit line configuration is generally employed as a bit line arrangement in order to reduce an influence of a noise upon a sensing operation. In the folded bit line configuration, a pair of bit lines are provided in parallel on one side of the sense amplifier. The storage data of the memory cell is read on one bit line of the pair. The other bit line is maintained at the level of a prescribed reference voltage (precharge voltage). A voltage difference between the pair of bit lines is amplified by the sense amplifier.
The amount of voltage change ΔV caused in a bit line before the sensing operation upon selection of the memory cell is given by the following expression (1), where a bit line capacitance is Cb, a capacitance value of the memory cell capacitor is Cs, and a potential difference between a storage node voltage and the precharge voltage is Vca.ΔV=Vca·Cs/(Cb+Cs)  (1)
In general, as the precharge voltage, a voltage VDD/2 is provided, which is ½ times a power supply voltage VDD of the memory cell. An H level and an L level of the storage data of the memory cell are a voltage VDD and a ground voltage (GND), respectively. Accordingly, Vca=VDD/2. As a typical example, when Cs=25 fF, Cb=100 fF, VDD=2V, and a cell plate voltage is 1V, the amount of voltage change (a read voltage) ΔV of this bit line is expressed by the following expression:ΔV=(25/125)·(2/2)=0.2 V.
In a general DRAM cell, two bit memory cells are formed in a unit active region. A bit line contact is shared between these two-bit memory cells. Adjacent unit active regions are electrically isolated by a field insulator film.
The bit line contact is provided for electrically connecting the memory cell active region to a corresponding bit line. In the folded bit line configuration, bit line contacts are generally provided for every other column (every other bit line). This is because the memory cell data must be read on only one of the pair of bit lines upon selection of one word line. Accordingly, there is created regularly a bit line contact-free region in a column direction.
A prior art document 1 (Japanese Patent Laying-Open No. 8-293587) discloses a layout for reducing a region free of bit line contact to arrange memory cells in higher density. In the prior art document 1, a memory cell active region is provided such that it crosses a bit line and a word line. In addition, a contact (a storage node contact) between a storage node of a memory cell capacitor and the active region is provided for a region corresponding to the region free of bit line contact. Through the provision of the storage node contact making use of the region free of bit line contact, a memory array area is utilized efficiently.
As a memory cell is shrunk, an area occupied by a memory cell capacitor is correspondingly reduced. Thus, capacitance value Cs of the memory cell capacitor decreases, and accordingly, the previously described read voltage ΔV is also reduced. As a result, a sensing operation cannot accurately be performed. In particular, when memory cells are highly integrated, the voltage level of memory power supply voltage VDD is reduced in order to ensure the reliability of a gate insulating film. Thus, read voltage ΔV lowers, and a sensing margin is decreased. As a result, it becomes difficult to perform an accurate sensing operation.
In the prior art document 1 described above, memory cells are arranged in the folded bit line configuration, and the memory cells could be arranged in high density. However, as a layout area occupied by the memory cell is reduced in accordance with an increased integration, bit line read voltage ΔV correspondingly decreases.
A prior art document 2 (Japanese Patent Laying-Open No. 7-130172) discloses a DRAM storing one bit of data with two memory cells for prevention of a decrease in operational margin, such as a decrease in read voltage, upon reduction in layout area occupied by a memory cell.
In the prior art document 2, a memory cell layout is similar to a general DRAM cell layout in which data of one bit is stored in one memory cell (one bit/one cell; a single mode). In addition, two word lines are concurrently selected to read memory cell data on each bit line of a pair of bit lines. Through the storage of complementary data in two memory cells, a voltage difference between the bit lines can be twice that in the single mode of one bit/one cell. Accordingly, a stabilized sensing operation can be achieved.
In a DRAM cell, a capacitor is utilized as a data storage medium. Thus, storage data may be lost through a leakage current. In order to prevent such a data disappearance, in a conventional DRAM, a refresh operation is performed, in which memory cell data is internally read, rewritten, and the original data is restored.
As a memory cell becomes shrunk, a capacitance value of a memory cell capacitor correspondingly decreases. Accordingly, an interval between refresh operations is required to be shorter. The shorter refresh intervals reduce the system processing efficiency, because the DRAM is generally inaccessible during the refresh operation. In addition, power dissipation for the refresh operation is increased.
When a one bit/two cell (twin cell) mode is employed, in which data of one bit is stored with two memory cells as described in the prior art document 2, a refresh interval can be longer. An area occupied by unit cell storing one-bit data, however, is increased since two memory cells are employed for storing data of one bit. If two conventional DRAM cell layouts are simply utilized to implement a twin cell storing data of one bit, a layout area by the twin cell of the data storage unit doubles. In this case, the storage capacity is ½ times compared to the typical single mode configuration in which data of one bit is stored in one memory cell. Thus, a twin cell mode DRAM with a large storage capacity cannot easily be realized.
Therefore, in order to realize a twin cell mode DRAM of a large storage capacity, a reduction in area occupied by the twin cell is necessary. In the memory cell layout described in the prior art document 1, the active region is provided in a direction crossing a bit line and a word line. In the prior art document 1, however, the storage node contact is arranged corresponding to the region free of bit line contact. Thus, a bit line contact and the storage node contact are alternately provided in the row direction. As a result, a regularity of a layout pattern is impaired.
Furthermore, an efficient utilization of a region free of bit line contact is simply intended. Memory cells are provided on alternate columns in the row direction. Therefore, in order to arrange the memory cells in high density, a further improvement in layout needs to be made.
In addition, in the prior art document 1, a typical folded bit line configuration is assumed. Thus, when the memory cell layout described in the prior art document 1 is employed for a twin cell configuration, memory cell data is merely transferred to only one of the pair of bit lines upon selection of one word line. In order to implement a twin cell mode, two word lines must be selected concurrently to transfer memory cell data to both bit lines in the pair. As a result, a problem arises that more current is consumed upon selection of word lines.